The present invention relates to a semiconductor memory device; and, more particularly, to a semiconductor memory device capable of minimizing a time required in accessing 4 bit data pre-fetched at a pipelatch.
A 2-bit pre-fetch scheme has been employed in a conventional semiconductor memory device and, recently, the use of a 4-bit pre-fetch scheme is being considered. In the 2-bit pre-fetch scheme, two data are simultaneously read out through different buses in response to one read instruction and stored at a pipelatch. Then, at a data output mode, the two data are outputted at a rising edge and a falling edge of a clock pulse, respectively. When reading out the two data, the two data can be read out in series or in parallel.
FIG. 1 provides a block diagram of a pipelatch unit 110 and an output driver 130 of a conventional semiconductor memory device.
In the conventional semiconductor memory device performing the 4-bit pre-fetch, 4 serial data inputs are loaded onto 4 global input/output lines (GIO) in response to one read instruction.
The pipelatch unit 110 of the conventional semiconductor memory device consists of 4 pipelatches, pipelatch less than 0:3 greater than , and receives data on multiplexer output lines, mxoutb, which are in a stand-by state at the outside of the pipelatch unit 110, when pipelatch-in signals, Pin less than 0:3 greater than , are transited to a low state xe2x80x9cLxe2x80x9d. Whether or not allowing data to be coupled into the pipelatch unit 110 is determined by the pipelatch-in signals, Pin less than 0:3 greater than .
In accordance with the conventional technology, the data on the multiplexer output lines, mxoutb, are accessed four times when they pass the pipelatch unit 110 and accessed one time at the output driver 130. That is, the data read out from a bank are accessed totally 5 times until being outputted to the outside of the semiconductor memory device.
At first, the above data are fed into one of the pipelatch less than 0:3 greater than  under the control of the pipelatch-in signals, Pin less than 0:3 greater than . Secondly, they are accessed in response to a start-odd start-even data output control signal, isoseb0_do. Thirdly, they are accessed under the control of a signal, isoseb1_rd, which accesss odd-numbered data in response to a start address and a signal, isoseb1_fd, which accesss even-numbered data in response to the start address. Fourthly, the data stored at the pipelatch less than 0:3 greater than  are coupled onto a rising edge output line, rdo, and a falling edge output line, fdo, in response to output control signals, rpout and fpout, so that the data stored at the pipelatch less than 0:3 greater than  are provided to the output driver 130 and then outputted to the outside at the output driver 130 under the control of a rising edge signal, fclk_do, or a falling edge signal, fclk_do, of a clock pulse.
Herein, the start-odd start-even data output control signal, isoseb0_do, is a control signal for accessing the data inputted to the pipelatch unit 110 according to whether or not the start address is an odd number or an even number.
In FIGS. 2A and 2B, there are described detailed circuit diagrams of a first-type and a second-type transmission gate shown in FIG. 1, respectively. Since the skilled person in the art can analyze the circuits by using the circuit diagrams described in FIGS. 2A and 2B, the detailed explanation for the circuits are omitted.
FIG. 3 shows a waveform diagram of simulation results at a first and a second accessing part in the pipelatch described in FIG. 1.
The conventional pipelatch receives data on the multiplexer output lines, mxoutb, when the pipelatch-in signal, Pin, is in a xe2x80x9cLxe2x80x9d state, and then doesn""t receive external data anymore if the pipelatch-in signal, Pin, is transited to a xe2x80x9cHxe2x80x9d state. That is, it is noted that the pipelatch provides the data onto a pre-rising edge output line, pre_rdo, or a pre-falling edge output line, pre_fdo, by multiplexing the data according to whether the start address is an even number or an odd number by using the start-odd start-even data output control signal, isoseb0_do.
FIG. 4 is a waveform diagram representing simulation results at parts for the accessing of odd-numbered data in the pipelatch and the output driver of FIG. 1.
In case the start address is 0, a first data on a first pre-rising edge output line, pre_rdo less than 0 greater than , of the pipelatch 110 is provided onto the rising edge output line, rdo, and the output driver 130 outputs the first data on the rising edge output line, rdo, during a rising edge, rclk_do, of a first clock pulse. Then, by the toggle of the signal, isoseb1_rd, for accessing odd data according to what the start address is, a third data on a second pre-rising edge output line, pre_rdo less than 1 greater than , is fed to the rising edge output line, rdo, and the output driver 130 outputs the third data on the rising edge output line, rdo, during a rising edge, rclk_do, of a second clock pulse.
FIG. 5 provides a waveform diagram representing simulation results at parts for the accessing of even-numbered data in the pipelatch and the output driver of FIG. 1.
In case the start address is 0, a second data on a first pre-falling edge output line, pre_fdo less than 0 greater than , of the pipelatch 110 is fed onto the falling edge output line, fdo, and the output driver 130 outputs the second data on the falling edge output line, fdo, during a falling edge, fclk_do, of the first clock pulse. Then, by the toggle of the signal, isoseb1_fd, for accessing even data according to what the start address is, a fourth data on a second pre-falling edge output line, pre_fdo less than 1 greater than , is coupled to the falling edge output line, rdo, and the output driver 130 outputs the fourth data on the falling edge output line, fdo, during a falling edge, fclk_do, of the second clock pulse.
That is to say, according to the conventional art, the data on the multiplexer output line, mxoutb, are accessed 4 times during they are passing the pipelatch unit 110 and accessed one time at the output driver 130. As a result, the data are totally accessed 5 times.
However, when accessing data 5 times at the pipelatch and the output driver, there occurs a problem of a data delay time lengthened. Namely, whenever accessing data, there is required a margin. For example, when allotting a margin of 300 ps for one-time accessing, a time of 1.5 ns is consumed for the five-time accessing. Further, since an address access time, tAA, includes the time required for data to pass the pipelatch, the address access time also becomes longer.
It is, therefore, an object of the present invention to provide a semiconductor memory device capable of minimizing a time required in accessing data at a pipelatch and an output driver.
In accordance with one aspect of the present invention, there is provided a semiconductor memory device capable of minimizing a data accessing time, comprising: a first control signal generation unit for outputting a first control signal generated by logically combining a pipelatch-in signal and a start-odd start-even data output control signal; a second control signal generation unit for outputting an odd control signal generated by logically combining an odd data enable signal for outputting odd-numbered data and a control signal for accessing the odd-numbered data in response to a start address, and outputting an even control signal produced by logically combining an even data enable signal for outputting even-numbered data and a control signal for accessing the even-numbered data in response to the start address; a first data accessing unit for accessing inputted data under the control of the first control signal outputted from the first control signal generation unit; a latch for temporarily storing data outputted from the first data accessing unit; and a second data accessing unit for secondly accessing the data stored at the latch and outputting secondly accessed data.
In accordance with another aspect of the present invention, the first control signal generation unit includes: an inverter receiving the pipelatch-in signal; a first NAND gate receiving an output of the inverter and the start-odd start-even data output control signal to thereby output a piseso signal; and a second NAND gate receiving the output of the inverter and an output of the first NAND gate to thereby output a pisose signal.
In accordance with another aspect of the present invention, the second control signal generation unit includes: an odd data accessing control signal producing sector for outputting the odd control signal generated by logically combining the odd data enable signal for outputting the odd-numbered data and the control signal for accessing the odd-numbered data in response to the start address; and an even data accessing control signal producing sector for outputting the even control signal created by logically combining the even data enable signal for outputting the even-numbered data and the control signal for accessing the even-numbered data in response to the start address.
In accordance with another aspect of the present invention, the first data accessing unit includes: a first transmission gate for outputting data on a first multiplexer even data output line under the control of the pisose signal; a second transmission gate for outputting data on a first multiplexer odd data output line under the control of the piseso signal; a third transmission gate for outputting data on a second multiplexer even data output line under the control of the pisose signal; and a fourth transmission gate for outputting data on a second multiplexer odd data output line under the control of the piseso signal, wherein output nodes of the first and the second transmission gates are connected to each other and output nodes of the third and the fourth transmission gates are attached to each other.
In accordance with another aspect of the present invention, the latch includes: a first plurality of inverters connected with the output node of the first transmission gate inversely and in parallel; and a second plurality of inverters connected with the output node of the third transmission gate inversely and in parallel.
In accordance with another aspect of the present invention, the second data accessing unit outputs data provided from the first plurality of inverters under the control of the pre-odd data output control signal and outputs data fed from the second plurality of inverters under the control of the post-odd data output control signal.
Therefore, by using circuits in accordance with the present invention, it is possible to substantially reduce the data accessing times at the pipelatch and the output driver in the semiconductor memory device.